In the data processing art including present day microprocessor technology, it is a known expedient to use pipelining on the primary I/O bus or channel which connect the main storage unit of the system to the CPU and various peripheral processors which are in turn connected to various I/O devices such as disk, display or printers. Such pipelining involves overlapped transactions on the I/O bus, i.e., a plurality of data transfers to and from various I/O devices or units or main storage may be overlapped on the primary I/O bus. In other words, the I/O bus needn't be locked into a single transaction; a first transaction may be initiated and before it is completed a second and a third transfer transaction involving the I/O bus may be initiated. Some typical patents describing such pipelining are Calta et al, U.S. Pat. No. 3,447,135, Peripheral Data Exchange; Dennis, U.S. Pat. No. 4,130,885, Packet Memory System for Processing Many Independent Memory Transactions Concurrently; Levy et al, U.S. Pat. No. 4,232,366, Bus for a Data Processing System with Overlapped Sequences; Dennis, U.S. Pat. No. 4,128,882, Packet Memory System with Hierarchical Structure; Cassarino, Jr. et al, U.S. Pat. No. 3,997,896, Data Processing System Providing Split Bus Cycle Operation; and the article "Synchronous LSSD Packet Switching Memory and I/O Channel", T. L. Jeremiah et al, published in the IBM Technical Disclosure Bulletin, Vol. 24, No. 10, March 1982.
To further maximize performance of the data processing systems, such common buses have been used to connect central processing units and various peripheral processing units to storage means having a plurality of interleaved storage units or banks. Such a system has been described as early as 1970 in the text "The Design of A Computer, The Control Data 6600", J. E. Thornton, Scott, Foresman and Company, Glenview, Ill., Published in 1970, particularly pages 44-56.
The interleaved storage means complements the pipelined common bus. Because storage operations are generally slower than the processors addressing the memory, the pipelined common bus gave processors the capability of sending addresses and other commands to memory or storage at a rate greater than basic storage units could handle. This resulted in the development of interleaved storage units wherein the address sent to storage from processors over the common bus addressed a plurality of interleaved memory units in sequence. As a result of this interleaving, each storage unit experiences a delay between addresses to it based upon the number of intermediate sequential interleaved storage units. As a result, the storage system can handle the addresses at a rate equivalent to the rate in which processors can provide such addresses.
While such interleaved storage systems have produced high performance data processing, we have noted in systems involving a common bus to which a plurality of processors may have access based upon conventional priority determining arrangements, there is some loss in efficiency in sequentially addressing the interleaved storage units every time access to the common bus is switched from one processor to another. While each processor may have its individual capability of addressing the interleaved storage units in the best sequence when there is a switch in access to the common bus, there tends to be a break in the sequence of addressing the interleaved storage units because of the transition of the sequence of addresses provided by processor originally having access and the processor to which access is switched. The reduced efficiency becomes particularly marked when there is a high frequency of switching access to the common bus from one processor to the other. In cases where switching is relatively frequent, there may be a reduction of up to 50% from the maximum address rate which the interleaved storage system is capable of.
The present invention provides a data processing system wherein efficiency in sequentially accessing interleaved storage units from a common bus is maximized even in systems having a high frequency of switching access to the bus between a plurality of processors.